library verilog;
use verilog.vl_types.all;
entity IOPADN_BI is
    port(
        N2POUT          : out    vl_logic;
        PAD             : inout  vl_logic;
        DB              : in     vl_logic;
        E               : in     vl_logic
    );
end IOPADN_BI;
